TSMC debuts N2 process utilizing nanosheet transistors

TSMC process roadmap. Credit: TSMC

TSMC at the company’s annual technology symposium for North America unveiled its next-generation N2 process powered by nanosheet transistors. N2 is scheduled to begin production in 2025, according to the pure-play foundry.

TSMC indicated N2 will feature nanosheet transistor architecture to deliver a full-node improvement in performance and power efficiency to enable next-generation product innovations from its customers. The N2 technology platform includes a high-performance variant in addition to the mobile compute baseline version, as well as comprehensive chiplet integration solutions.

TSMC’s N2 will be able to offer a 10-15% speed improvement at the same power over N3, or 25-30% power reduction at the same speed, the company said.

a Reuters report quoted TSMC executives as saying the company will receive ASML’s high-NA EUV chipmaking tools in 2024.

At the symposium, TSMC also disclosed its N3 technology will feature the TSMC FINFLEX architectural innovation offering, which the company claims offers “unparalleled flexibility for designers.” The FINFLEX architectural feature offers choices of different standard cells with a 3-2 fin configuration for ultra performance, a 2-1 fin configuration for power efficiency and transistor density, and a 2-2 fin configuration providing a balance between the two.

With its proprietary FINFLEX architecture, “customers can create SoC designs precisely tuned for their needs with functional blocks implementing the best optimized fin configuration for the desired performance, power and area target, and integrated on the same chip,” TSMC said.

In addition, TSMC disclosed it is developing N6e designed to provide the computing power and energy efficiency required by edge AI and IoT devices. N6e will be based on TSMC’s 7nm process and is expected to have three times greater logic density than N12e. It will serve as a part of TSMC’s ultra-low power platform, a portfolio of logic, RF, analog, embedded nonvolatile memory and power management IC solutions aimed at applications in edge AI and the IoT.

Two customer applications of the TSMC-SoIC chip stacking solution were also showcased at the symposium: a SoIC-based CPU employing chip-on-wafer (CoW) technology to stack SRAM as a Level 3 cache; and an intelligence processing unit stacked on top of a deep trench capacitor die using wafer-on-wafer (WoW) technology.

TSMC noted that with N7 chips in production for both CoW and WoW, support for N5 technology is scheduled for 2023. And to meet customer demand for SoIC and other TSMC 3DFabric system integration services, TSMC continued, “the world’s first fully automated 3DFabric factory is set to begin production in the second half of 2022.”

Located in Chunan, northern Taiwan, TSMC’s fully-automated 3DFabric factory site will be where the company commercializes its SoIC technology. TSMC CEO CC Wei disclosed in June 2021 plans to have five fabs dedicated to providing its 3DFabric advanced packaging solutions by the end of 2022.

TSMC advanced process roadmap
Source: Company

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